N2: TSMC wants to remain the best chip manufacturer with nanosheet transistors from 2025

The chip contract manufacturer Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) outlined its manufacturing plans beyond current manufacturing techniques with 5-nanometer structures at the Amsterdam EU Technology Symposium. Of particular interest was the next major step in transistor technology, which will be introduced with the N2 process from the 2 nm generation: Nanosheet transistors as a replacement for the FinFETs that have been common up to now.

According to their own statements, this technology has been in development for 15 years and they want to use the technology, which is also more commonly referred to elsewhere as Gate-All-Around (GAA), in mass production from 2025. The so-called risk production for small series or prototypes should already start in the factory at the end of 2024.

If everything goes according to plan, the 2-nanometer process will compete with Intel’s “Intel 20A” technology with RibbonFET (another marketing term for GAA). At the Technology Symposium, TSMC was confident that it would still be able to deliver the most advanced, best transistors – but according to which standards remains open. Because Intel wants to produce RibbonFETs with the “Intel 20A” manufacturing technology and the option of power vias as early as 2024.

TSMC’s counterparts are the backside power vias, in which the metal planes for the power supply are attached to the underside of the silicon and are therefore separated from the signal lines on its upper side. This separation is intended to improve the switching speed of the transistors. TSMC’s Senior Vice President Business Development Dr. Kevin Zhang explains in a small group that this is also driving up the processing steps per wafer significantly, but he did not want to reveal exact figures for the process that is still in development.



The improvements from N3E to N2 are said to be up to 26 percent more performance or 25 percent less power consumption. For processors and graphics chips with higher voltages, TSMC promises a performance increase of 15 percent.

The PPA information, which is intended to illustrate the progress compared to the standard N3E process, was calculated without backside power vias, Zhang said. PPA stands for Performance, Power, Area and describes the magic triangle of transistor production, on the edges of which the points are moved back and forth. TSMC does not plan to also offer backside power vias for coarser processes, i.e. N3, N4, N5 and higher. And even with N2, they are just an option, not a mandatory part of the technology.

The advantages that TSMC ascribes to the N2 nanosheet transistors compared to its own upcoming N3E process can also be seen without backside power vias. Significantly higher switching speeds are possible, especially at low voltage points, for example a plus of 26 percent at 0.55 volts, alternatively the power consumption drops by 24 percent at the same clock frequency.

At higher voltages, which are important for processors and graphics chips with maximum performance and turbo functions, the performance advantage melts down to 15 percent, but the advantage in terms of power consumption remains almost the same at 25 percent – ideal for those who are increasingly limited by power consumption chips in the high-end market.


More from c't magazine

More from c't magazine


More from c't magazine

More from c't magazine


(csp)

To home page

Leave a Comment