If the transition from 7 nm to 4 nm was done gradually, the one leading from 4 nm to 3 nm represents a much greater technological leap. A leap that is both more difficult technically and financially, but which could above all cause a slowdown in an industry currently overheating.
The year 2023 will not be the year of mass engraving in 3 nm. If the A17 chip of the future iPhone 15 Pro is undoubtedly already in pre-production in the very secret factories of TSMC, this should be the exception which confirms the rule. While Apple has immensely deep pockets and a small portfolio of chips, players like Qualcomm and MediaTek should wait a little longer before taking the plunge.
Read also: TSMC still going strong: 3 nm per hour and a 35 billion dollar factory (March 2021)
It must be said that 3 nm processes – an important plural – are not nodes (the jargon to talk about fine engraving) innocuous. Whether at Samsung, where node is based on a new generation of transistors. Or at the champion TSMC, where the N3 process remains on FinFET transistors, but where all production is redesigned… and where prices are exploding and yields are falling.
Multiple 3nm processes
Apart from the fact that there is no international standard to qualify nodes production (everyone counts their nanometers in their corner), the processes are different in approach. For TSMC, where the 6 nm was the extension of the 7 nm and the 4 nm that of the 5 nm, the 3 nm is indeed a major step. which requires that the chips that need to be burned into this nodeor, from the outset, designed for this.
Read also : How far will chip miniaturization go? Samsung promises 1.4nm transistors in 2027 (Oct 2022)
Even more restrictive is Samsung’s 3nm. While Korean was proud to have been the first on this finesse of circuit design, Samsung also specified that this node would be the first to use the new generation of so-called “ Gate All Around ” Where GAAFET at Samsung (Nano sheet at TSMC and nanoribbon at Intel). The successor to the FinFET that has been in service for more than a decade, these new transistors require much deeper design work.
The two manufacturing methods of TSMC and Samsung have this in common that they massively use the famous extreme ultraviolet (EUV) lithography machines. These overpriced machines (around 150 million euros each!) are the ones that have succeeded in bringing the world of semiconductors below 8 nm. Used for some steps from 7 nm in addition to DUV machines (deep ultraviolet) classics, their use is much more intensive as the fineness of engraving is reduced.
If on the one hand, they limit the number of passages of the silicon wafer which can lead to savings (fewer stages = fewer errors = better yields), the fact that they are now used at all stages production of the chip inflates the price of wafers (the usage time of each machine influences the final price). The wafers are the famous “wafers” of silicon on which the circuits of future chips are engraved.
Price inflation
Measuring 300mm in diameter, the wafer said “12 inch” introduced in 2001/2022 is the support for the most modern chips – there are still production lines in 150 mm (6 inches) and 200 mm (8 inches) for the least expensive chips. If the silicon wafer has a fixed price as a blank medium, its price varies enormously depending on the etching process used to “write” the components on its surface. And the node 3nm has pushed prices even higher than in the past, with an estimated price of $20,000 per wafer.
Read also : TSMC: the 3 nm engraving factory will be operational in the second half of 2022 (Nov. 2020)
If we compare to the 5nm at $16,000 and the $10,000 of the 7nm, the price hurts. All the more so since the 60% additional cost between 5 nm and 7 nm still made it possible to burn up to 80% more chips (of the same number of transistors). While the transition from 4/5 nm (same process) to 3 nm only allows an increase in the number of transistors of only 30%. Blame it on the fact that not all parts of the chips can benefit equally from downsizing circuits – CPU cores are downsized more easily than on-board SRAM memory.
Moreover, the inflation of the tariffs of the wafers is not the only one to hurt. The change of node, even the change of structure of the transistors (Samsung GAAFET and its equivalent Nanosheet at TSMC) implies other expenses. In particular those of semiconductor design software from Cadence and Synopsys. Far from being anecdotal, these essential tools for the production of chips are one of the reasons (along with the blocking of EUV machines from the Dutch ASML) why China cannot produce cutting-edge processors.
Just look at the inflation in the cost of chip design: before you even hit the ” start » of industrial production, the design of a 5 nm chip could have cost half a billion euros! And it could be even worse for the 3 nm GAAFET… Which doesn’t mean that production is going to be impossible. Because if the deployment could be slowed down, the manufacturers are up against the wall.
A price war in sight?
In the world of advanced manufacturing processes, TSMC has the edge over Samsung. It is indeed the Taiwanese which produces 90% of the chips engraved at 7 nm or less. An ultra-dominant position that pushes the Korean to constantly play the price card to attract customers. But while TSMC was in a strong position during the shortage period to keep prices high, the tide could turn. Because with the little gain in density brought by 3 nm (called N3) compared to 5 nm, the $20,000 per wafer would only be interesting in the case of chips with very (very!) high added value. According to analysts interviewed by our colleagues at fudzilla, this high cost would entice the chip designers you know – AMD, Qualcomm, MediaTek, etc. – to wait and concentrate on the nodes 4 and 5 nm. Leaving the field open to Apple to pay the price of gold for 3 nm for its chips.
Only here, if Apple is a major customer with very high volume (and high added value), it will not be enough to run the factories at full speed. However, the factories are there, the investments have been made. And the only way to make the tens of billions invested profitable is to rotate them. This is why, still according to analysts, TSMC could trim its margin and lower its prices to attract customers. This will have the effect of putting pressure on Samsung, a challenger in the field, to practice the lowest possible prices.
Read also : IBM and Samsung have developed the transistors of the future (Dec. 2021)
We conclude that if the industry is dragging its feet a little for the launch of the 3 nm, which should be the exclusivity of Apple at first, the pressure on TSMC and Samsung to make their colossal investments profitable should push them to lower prices as soon as possible. But this organic slowdown could weigh on the future of chip design. With a public roadmap that stops at 2 nm at TSMC (1.8 nm at Intel for its node Intel 18) and the passage of wafers from 300 mm to 450 mm still postponed indefinitely, the “friction” currently caused by the node 3 nm could slow down, for a time, the industry in its developments. An industry which is, in certain areas such as memory, in full overheating.
