The fourth generation of scalable Xeon processors is in the starting blocks: Intel is planning 52 different models of the Xeon SP Gen 4 aka Sapphire Rapids with 8 to 60 cores. They cost from 415 to 17,000 US dollars, including many special types for IoT and high-performance computing. But the magic ingredient – or, depending on your point of view, the emergency nail – are integrated accelerator functions, with which Intel wants to relieve the general-purpose computing cores and promise high computing power.
The variety of models is confusing at first glance. Depending on their performance, the Xeons are classified as Platinum (8400), Gold (6400), Silver (5400) and Bronze (3400) and, more recently, Max (9400). The second digit of the model designation stands for the generation and is therefore always “4”. A number of models also have an abbreviation for the intended purpose: the “H” stands for the 8-socket version, the “U” for 1-socket Xeons. There is also an “S” for storage and “N” for networks and 5G. General 2-socket CPUs can just have one number like the Max versions. The 8-socket H variants with all accelerators are by far the most expensive – mainly because there is no competition from AMD in this segment; the Epyc only runs individually or in pairs.
The new Xeons are designed to curb the growth of Epyc’s market share in data centers and servers. Intel has finally modernized the Xeon platform and, in addition to more, also offers faster memory in the DDR5 standard, CXL and Optane support and up to 80 PCIe 5.0 lanes for SSDs and accelerator cards. The processors manufactured with “Intel 7” technology, i.e. in 10-nanometer production, consume between 125 and a maximum of 350 watts under full load, depending on the model, and are therefore almost 30 percent more power hungry than their predecessors under full load.
Xeon Chief Architect Ugonna Echeruo (left) and Jeff McVeigh (right), Head of Intel’s Supercomputing Group, proudly presented the new Xeon processors.
Choice of three chips
Intel initially produces three different chips. For starters, it’s a monolithic 34-core aka “Medium Core Count” (MCC). On the other hand, Intel uses a design with only 15 cores for the high-end variants, but still calls it “Extreme Core Count” (XCC). Because up to four of them are connected by the “Embedded Multi-Die Interconnect Bridge” (EMIB).
The third Xeon variant is intended for the “Xeon CPU Max Series” and, in addition to the DDR5 memory controllers, also has some for 64 GB of the high-speed HBM2e memory. The Xeon CPU Max are intended for high-performance computing, such as in the supercomputer Aurora, and for applications that require extremely high transfer rates, and can also be operated without DDR5 memory. Alternatively, the HBM serves as a fast, transparent cache for the main memory or – with some programming effort – as a separate memory area. In the Stream Triad memory benchmark, the Xeon Max achieves a transfer rate that is three and a half times higher than the models with DDR5 memory, according to Intel. In real applications, this would still be an increase of up to 2.3 times.
While the Xeon Max will only be validated for 1 and 2 socket systems, the monolithic MCC versions will be available for up to four sockets and the XCC variants will also be available for 8 socket systems.
