The chip applicator TSMC is on schedule with the development of its 2-nanometer process generation. The manufacturer is currently touring with the Technology Symposium, including current insights into process development.
From the end of 2025, TSMC wants to mass-produce chips with 2 nm structures. Apple is traditionally the first major buyer of iPhone and MacBook processors.
So far, TSMC has only given general projections for the so-called PPA values. This stands for performance, power, area and gives a rough overview of the improvements of a new manufacturing process.
In the meantime there are more concrete figures based on an implementation in a smartphone processor, calculated for an ARM CPU core of the Cortex-A715 type: Compared to the 3 nm process N3E, the speed should increase by a good 16 percent thanks to shorter switching times with the same electrical power consumption. Alternatively, the electrical power consumption can be reduced by 37 percent at the same speed. The transistor density should increase by at least a factor of 1.15.
The comparison applies to high-performance libraries when the transistors of the CPU core are two to three fins high. In standard cells with one or two fins, the lead should be 13 percent (speed) or 33 percent (power consumption).
GAAFETs are replacing FinFETs
With N2, TSMC introduces transistors with a “gate all around” structure – so-called GAAFETs as a replacement for FinFETs, called nanosheets by the manufacturer. Samsung has already taken this step with its 3 nm generation, but has not yet announced any major customers for 3 nm chips. Intel wants to introduce the technology under the name RibbonFETs with the 20A generation as early as 2024 if everything goes according to plan.
The new structure is necessary to further shrink the transistors. TSMC and Intel couple the switch to new lithography systems that expose with extreme ultraviolet wavelengths at a high numerical aperture (high-NA EUV). Because these machines are taller than previous EUV systems, they require new semiconductor factories. ASML wants to deliver the high-NA EUV systems from 2024 – Intel has secured the first contingents.
Another thing they have in common is the plan to supply chips with electricity from below in the future: the signal connections run on the top, and the electrical wiring is on the bottom. This step is intended to improve the signal quality and the power supply by reducing unwanted voltage reductions (IR drops).
TSMC speaks specifically of an additional 10 to 12 percent increase in speed through the Backside Power Rails. Logic blocks within a chip design could shrink by another 10 to 15 percent. The technology is primarily intended for high-performance chips, such as CPUs and GPUs, and is scheduled to be introduced in 2026.
TSMC’s roadmap for the 3nm generation. Attention: The improvements of N3P and N3X each refer to N3 and do not add up.
(Bild: Taiwan Semiconductor Manufacturing Co., Ltd., via SemiWiki)
New 3nm processes
Until then, there will be a whole series of new 3 nm processes. Mass production of N3E is scheduled to start in the second half of 2023. Due to a higher flexibility in the design rules, a higher distribution than with N3 is expected. In addition, the speed should increase by 5 percent. N3P grows another 5 percent. Alternatively, companies can invest in improvements in a 5-10 percent reduction in electrical power consumption. Transistor density is expected to increase by 4 percent.
N3X is intended for high-performance chips with higher voltages. At 1.2 volts, the speed should increase by another 5 percent. Compared to the N3, the performance plus would be 15 percent. TSMC has scheduled series production in N3P for the second half of 2024, N3X will follow in 2025. There should also be N2P and N2X offshoots in the 2 nm generation.
AMD and Nvidia are rumored to want to wait for N3X, until they migrate to TSMC’s 3nm generation. By then, 5nm-based manufacturing processes, including N4, should be in place.
Based on N3P, the chip order manufacturer is also developing the automotive-specific processes N3AE (N3 Auto Early) and N3A (N3 Auto Ready). TSMC wants to work with car manufacturers for a comprehensive certification chain, but in the case of N3A this will not result in series production until 2026. The technology is intended, for example, for autonomously driving cars.
(mma)
